This invention relates to electronics, in general, and to integrated circuits and methods of operation, in particular.
Many integrated circuits are highly sensitive to voltage spikes or surges caused by Electro-Static Discharge (ESD), Electrical Fast Transients (EFT), and lightning. Additionally, voltages that exceed a maximum voltage rating of an integrated circuit may be accidentally applied to the integrated circuit, thereby damaging the integrated circuit. Accordingly, these highly sensitive integrated circuits must be protected from the voltage spikes or surges. One technique to protect the highly sensitive integrated circuits is to connect a separate or discrete transient over-voltage protection component in series with the highly sensitive integrated circuit. These discrete techniques, however, are expensive and cumbersome because they require an additional component.
Another technique to protect the highly sensitive integrated circuits includes integrating a transient over-voltage protection sub-circuit into the integrated circuit. The existing integrated transient over-voltage protection techniques suffer from several problems. For example, standard ESD protection structures are not capable of protecting sensitive circuitry from steady-state over-voltage conditions because ESD circuits only protect against transient voltage spikes of short duration. Additionally, many over-voltage detection techniques, such as diode clamping, may still allow unacceptably high voltages to be transferred to the sensitive circuitry before the over-voltage protection is activated.
Accordingly, a need exists for an integrated circuit and method of operation that is protected from short-term and long-term voltage spikes or surges where such protection is integrated into the integrated circuit. For example, the Universal Serial Bus (USB) specification requires a USB transceiver to withstand a continuous short-circuit of an over-voltage that exceeds the supply voltage used in the USB transceiver. For example, the USB specification requires the input/output (I/O) terminals of a USB transceiver to survive a continuous short-circuit to 5.25 volts, but present semiconductor processes used to implement USB transceivers may only be rated to a maximum voltage of 3.6 volts or less. Furthermore, the USB transceiver is required to withstand the continuous short-circuit of the over-voltage for a minimum of 24 hours without degrading the performance of the USB transceiver. Moreover, the USB specification recommends that USB transceivers be designed to withstand such over-voltage short-circuits indefinitely. Many other serial data communication standards also face similar reliability concerns.
In accordance with the principles of the invention, a first embodiment of an integrated circuit comprises a first node; a second node; a resistor coupling together the first and second nodes; a comparator having two inputs and an output, a first one of the two inputs coupled to the resistor and the first node; and a three-terminal device having a first terminal coupled to the second node and the resistor and having a second terminal coupled to the output of the comparator.
Furthermore, in accordance with the principles of the invention, a second embodiment of an integrated circuit comprises a first circuit; a first node; and a second circuit coupling the first circuit to the first node. In this embodiment, the first circuit operates off of a supply voltage, and the second circuit detects a voltage magnitude of a signal at the first node and reduces the voltage magnitude of the signal to equal a voltage magnitude of the supply voltage before transmitting the signal to the first circuit.
In accordance with the principles of the invention, a third embodiment of an integrated circuit comprises a first node; a second node; a first resistor coupling together the first and second nodes; a first three-terminal device being of a first type, a first terminal of the first three-terminal device coupled to the first resistor and the first node; a second three-terminal device being of the first type, a first terminal of the second three-terminal device coupled to a first substantially constant voltage, a second terminal of the second three-terminal device coupled to a second terminal of the first three-terminal device and to a third terminal of the second three-terminal device; a third three-terminal device being of a second type, a first terminal of the third three-terminal device coupled to a second substantially constant voltage, a third terminal of the third three-terminal device coupled to a third terminal of the first three-terminal device; a fourth three-terminal device being of the second type, a first terminal of the fourth three-terminal device coupled to the second substantially constant voltage, a second terminal of the fourth three-terminal device coupled to a second terminal of the third three-terminal device and to a third terminal of the fourth three-terminal device; a fifth three-terminal device being of the second type, a first terminal of the fifth three-terminal device coupled to the second substantially constant voltage, a second terminal of the fifth three-terminal device coupled to the third terminals of the first and third three-terminal devices, a third terminal of the fifth three-terminal device coupled to the first resistor and to the second node; a sixth three-terminal device being of the first type, a first terminal of the sixth three-terminal device coupled to the third terminals of the first and third three-terminal devices and to the second terminal of the fifth three-terminal device, a second terminal of the sixth three-terminal device coupled to the first substantially constant voltage, a third terminal of the sixth three-terminal device coupled to the second terminals of the third and fourth three-terminal devices and to the third terminal of the fourth three-terminal device; and a second resistor coupling together the second terminals of the first and second three-terminal devices and the third terminal of the second three-terminal device to the second terminals of the third and fourth three-terminal devices and to the third terminals of the fourth and sixth three-terminal devices.
In accordance with the principles of the invention, an embodiment of a method of operating an integrated circuit comprises detecting a signal at a first node, the signal having a first voltage magnitude; comparing the first voltage magnitude to a reference voltage magnitude; if the first voltage magnitude is less than the reference voltage magnitude, transferring the signal with the first voltage magnitude to a second node; and if the first voltage magnitude is greater than the reference voltage magnitude, reducing the first voltage magnitude to a second voltage magnitude less than or equal to the reference voltage magnitude; and transferring the signal with the second voltage magnitude to the second node.